computer organisation – basics

Decoded instruction is stored in IR. The MAR (memory address register) is used to hold the address of the location to or from which data are to be transferred. MDR(memory data register) contains the data to be written into or read out of the addressed location. ISP stands for Instruction Set Processor. processor BUS is used to connect the various parts in order to provide a direct connection to the CPU

Multiplexer is used to choose between incrementing the PC or performing ALU operations. The registers, ALU and the interconnection between them are collectively called as data path. D flip flop is used to store data in registers. During the execution of the instructions, a copy of the instructions is placed in the cache. For a given FINITE number of instructions to be executed, superscalar architecture of the processor provides faster execution. An optimizing compiler is designed for increasing the operation speed of the processor by reducing the time taken to compile the program instructions. The ultimate goal of a compiler is to, reduce the clock cycles for a programming task

SPEC – System Performance Evaluation Corporation

CISC – Complex Instruction Set Computer

RTN – Register Transfer Notation

ANSI – American National Standards Institute

When Performing a looping operation, the instruction gets stored in the cache. The average number of steps taken to execute the set of instructions can be made to be less super scaling. If the instruction, Add R1,R2,R3 is executed in a system which is pipe-lined, then the value of S is 1 (Where S is term of the Basic performance equation), s is the number of steps for execution

RTN stands for Register Transfer Notation, way of writing the assembly language code with the help of register notations. The two phases of executing an instruction are  Instruction fetch and instruction execution . The Instruction fetch phase ends with Decoding the data in MDR and placing it in IR

While using the iterative construct (Branching) in execution, branch instruction is used to check the condition. When using Branching, the usual sequencing of the PC is altered. A new instruction is loaded which is called as branch target. The main virtue for using single Bus structure is, Cost effective connectivity and ease of attaching peripheral devices. To extend the connectivity of the processor bus we use PCI bus. IBM developed a bus standard for their line of computers ‘PC AT’ called ISA. The bus used to connect the monitor to the CPU is SCSI bus.

Z register Connected to the Processor bus is a single-way transfer capable. Z register can interact with the processor BUS only. In multiple Bus organisation, the registers are collectively placed and referred as register file. The main advantage of multiple bus organisation over single bus is, Reduction in the number of cycles for execution. The ISA standard Buses are used to connect, Hard disk and Processor. The location to return to, from the subroutine is stored in link resgister. The order in which the return addresses (subroutine) are generated and used is LIFO. In case of nested subroutines the return addresses are stored in Processor stack. The appropriate return addresses is obtained by the help of stack pointer in case of nested routines. In parameter passing of subroutine, the data can be stored on any of the storage space. The most efficient way of handling parameter passing is by using General purpose registers

DOS – Disk operating system

High level programming languages

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Basic electronics

Digital electronics